Dr. Matthias Gries


München, Germany

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Dr. Matthias Gries

At Cyberus Technology, I analyze confidential computing CPU technologies with implications on cloud and edge use cases, usability, interplay with complementary security approaches, as well as technology readiness subject to regulatory conditions.

From 2015 to 2024, as principal R&D engineer at Huawei Technologies' Advanced Computing team in München, Germany, I was responsible for developing technologies for CPU architectures and the design of memory and Arm AArch64 subsystems, as well as their SoC-level integration and software enablement for scientific computing. From 2007 to 2014, I developed integrated hardware-software technologies for memory subsystems, manycore, and resource management at Intel in Braunschweig, Germany. Before, at Infineon Technologies in Munich, Germany, I developed programmable microarchitectures and their programming views for network applications at the Corporate Research and Communication Solutions departments. I was a post-doctoral researcher in the Mescal group at UC Berkeley from 2002 to 2004 working on methods for ASIP design. I received my Ph.D. (Dr. sc. techn.) from ETH Zurich, Switzerland, in 2001 for my work on QoS network processors. My interests include CPU architectures, methods and tools for developing compute platforms, ASIPs, system-level design, and the analysis of MP-SoCs.

Overview

Software

  • Arm AArch64 software ecosystem enabling: Performance characterization and optimization of sparse linear algebra frameworks (see AHUG presentation 2023)
  • Arm AArch64 software ecosystem enabling: BeeGFS filesystem, together with ThinkParQ (see 2022 whitepaper); HPC applications (GROMACS, GPAW and others)
  • Persistent Memory: exposing Non-Volatile Memory (NVM) as durable random access memory to applications; Intel Labs, complemented by NOVOS project at TU Cottbus (link to page at BTU), 2012 - '14
  • SystemClick: SystemC and CRACC combined for design space exploration at Infineon (see DAC'08 paper)
  • CRACC embedded software development framework at Infineon (see DAC'05 paper)
  • Tipi: Mescal architecture development system at UC Berkeley (2004)
  • EXPO: Design space exploration tool at ETH Zurich (see DAC'02 paper)
  • DRAM models for SimpleScalar CPU micro-architecture simulator, at ETH Zurich (2000)

Hardware

  • DIMM-NDP concept design of near-data processing on memory modules using standard DRAM chips, MRC Huawei Technologies, 2017 - '18
  • In-system prototyping with QPI-FPGA for mixed DRAM - NVM (such as Phase Change and Spin-Transfer Torque memories) subsystems, Intel Labs, 2012 - '14
  • Realtime DDR3 Programmable Memory Traffic Analyzer, Intel Labs, FPGA-based prototype of DIMM interposer (see Intel's press kit for the Research@Intel Europe event 2011, demonstration in computing zone)
  • Single-chip Cloud Computer (SCC), Intel Labs, 45nm silicon experimental processor (see ISSCC'10 paper "A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS" aka. Single-chip Cloud Computer [SCC])
  • Network Optimized Versatile Architecture (NOVA), Infineon Technologies, FPGA prototype (see DATE'07 paper and CeBIT'06 trade fair demonstration) 
  • Book on Mescal methodology for ASIP design (Application-Specific Instruction Processor), UC Berkeley, 2005

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