Matthias Gries E-mail:

Postal Address:  Matthias Gries Intel Labs Microprocessor and Programming Research (MPR) Theodor-Heuss-Straße 7 38122 Braunschweig, Germany WWW http://www.mgries.net

I joined Intel Labs Braunschweig (aka. Intel Germany Research Center IGRC) in April 2007. I am working on memory subsystem and resource management solutions. Before, at Infineon Technologies in Munich, Germany, I dealt with microarchitectures for network applications at the Corporate Research and Communication Solutions departments. I was a post-doctoral researcher in the Mescal group at UC Berkeley from 2002 to 2004 working on methods for ASIP design. I received my Ph.D. ("Dr. sc. techn." to be precise) from ETH Zurich, Switzerland, in 2001 for my work on QoS network processors. My interests include architectures, methods and tools for developing x86 platforms, ASIPs, system-level design, and analysis of MP-SoCs.

• Highlights
• Projects
• at Intel Labs Germany
• at Infineon Technologies
• at UC Berkeley
• at ETH Zurich
• Curriculum Vitae
• Publications
• Software
• Hardware
• Misc.

Highlights

• ISSCC 2010: "A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS" aka. Single-chip Cloud Computer (SCC)
• CeBIT'06 trade fair demonstration
• Book on Mescal methodology for ASIP design

Software

• SystemClick: SystemC and CRACC combined for design space exploration at Infineon (see DAC'08 paper)
• CRACC embedded software development framework at Infineon (see DAC'05 paper)
• Tipi: Mescal architecture development system at UC Berkeley (2004)
• EXPO: Design space exploration tool at ETH Zurich (2001)
• DRAM models for SimpleScalar at ETH Zurich (2000)

Hardware

• Single-chip Cloud Computer (SCC), Intel Labs, 45nm silicon prototype (see ISSCC'10 paper)
• Network Optimized Versatile Architecture (NOVA), Infineon Technologies, FPGA prototype (see DATE'07 paper)