System-level design of a network processor for access networks,
focusing on IntServ- and DiffServ-like QoS service schemes. Apart from
implementing policing, queue management, and packet scheduling policies
in ETH's MOSES framework I also implemented DRAM and memory controller
models in Simplescalar for evaluating controller policies.
L. Thiele, S. Chakraborty, M. Gries, S. Künzli: A Framework for Evaluating Design Tradeoffs in Packet Processing Architectures, 39th Design Automation Conference (DAC 2002), New Orleans LA, USA, pages 880-885, June 2002
L. Thiele, S. Chakraborty, M. Gries, A. Maxiaguine, J. Greutert: Embedded Software in Network Processors - Models and Algorithms, First Workshop on Embedded Software (EMSOFT), Lake Tahoe CA, USA, LNCS 2211, Springer-Verlag, pages 416-434, Oct. 2001
K. Strehl, L. Thiele, M. Gries, D. Ziegenbein, R. Ernst, J. Teich: FunState - An Internal Design Representation for Codesign, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.9, no. 4, pages 524-544, Aug. 2001
M. Gries: The Impact of Recent DRAM Architectures on Embedded Systems Performance, Euromicro'2000, 26th Symposium on Digital Systems Design, Maastricht, Netherlands, vol. 1, pages 282-289, Sep. 2000