B. Dietrich, D. Goswami, S. Chakraborty, A. Guha, M. Gries: Time Series Characterization of Gaming Workload for Runtime Power Management, IEEE Transactions on Computers, vol. 64(1), pages 260-273, Jan. 2015
M. Gries, U. Hoffmann, M. Konow, M. Riepen: SCC: A Flexible Architecture for Many-Core Platform Research, Novel Architectures Column, IEEE/AIP Computing in Science and Engineering, vol. 13(6), pages 79-83, Nov./Dec. 2011, draft pdf: 2011-CiSE-SCC-draft.pdf
J. Howard, S. Dighe, S.R. Vangal, G. Ruhl, N. Borkar, S. Jain, V. Erraguntla, M. Konow, M. Riepen, M. Gries, G. Droege, T. Lund-Larsen, S. Steibl, S. Borkar, V.K. De, R. Van Der Wijngaart: A 48-Core IA-32 Processor in 45nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling, IEEE Journal of Solid State Circuits (JSSC), vol. 46(1), pages 173-183, Jan. 2011
S. Sonntag, M. Gries, C. Sauer: SystemQ: Bridging the Gap between Queuing-based Performance Evaluation and SystemC, Design Automation for Embedded Systems, Springer NL, vol. 11(2-3), pages 91-117, Sept. 2007
M. Gries, K. Keutzer (editors): Building ASIPs: The Mescal
Methodology, Springer, 375 pages,
June 2005, ISBN: 0-387-26057-9
abstract,
authors, and table of contents
C. Sauer, M. Gries, J.I. Gomez, K. Keutzer: Towards a Flexible Network Processor Interface for RapidIO, Hypertransport, and PCI-Express, Network Processor Design: Issues and Practices, volume 3, Editors: M. Franklin, P. Crowley, H. Hadimioglu, P. Onufryk, pages 55-80, Morgan Kaufmann Publishers, Feb. 2005
M. Gries: Methods for Evaluating and Covering the Design Space during Early Design Development, Integration, the VLSI Journal, Elsevier, vol. 38(2), pages 131-183, 2004
M. Gries, C. Kulkarni, C. Sauer, K. Keutzer: Exploring Trade-offs in Performance and Programmability of Processing Element Topologies for Network Processors, Network Processor Design: Issues and Practices, volume 2, Editors: P. Crowley, M. Franklin, H. Hadimioglu, P. Onufryk, Morgan Kaufmann Publishers, pages 133-158, Nov. 2003
L. Thiele, S. Chakraborty, M. Gries, S. Künzli: Design Space Exploration of Network Processor Architectures, Network Processor Design: Issues and Practices, Editors: P. Crowley, M. Franklin, H. Hadimioglu, P. Onufryk, Morgan Kaufmann Publishers, pages 55-89, Oct. 2002, Draft: pdf at ETHZ: TCGK02c.pdf
K. Strehl, L. Thiele, M. Gries, D. Ziegenbein, R. Ernst, J. Teich: FunState - An Internal Design Representation for Codesign, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.9, no. 4, pages 524-544, Aug. 2001, Draft: pdf at ETHZ: TVLSI_STG_01.pdf
M. Gries: Algorithm-Architecture Trade-offs in Network Processor Design, Ph.D. thesis, Computer Engineering and Networks Laboratory (TIK), ETH Zurich, Switzerland, ETH Diss. No. 14191, Shaker Verlag Aachen, Germany, July 2001, ISBN 3-8265-9044-9, pdf: diss_gries.pdf, pdf with marks and links: diss_gries_hyper.pdf; Abstract
M. Gries: Modeling a Memory Subsystem with Petri Nets,Hardware Design and Petri Nets, Kluwer Academic Publishers, Editors: Alex Yakovlev, Luis Gomes, Luciano Lavagno, pages 291-310, March 2000, ISBN 0-7923-7791-5, pdf at ETHZ: Gri00a.pdf
Best paper: N. Ioannou, M. Kauschke, M. Gries, M. Cintra: Phase-based Application-driven Hierarchical Power Management on the Single-chip Cloud Computer, 20th int. conference on Parallel Architectures and Compilation Techniques (PACT), pages 131-142, Oct. 2011
B. Dietrich, S. Nunna, D. Goswami, S. Chakraborty, M. Gries: LMS-based Low-Complexity Game Workload Prediction for DVFS, 28th IEEE Int. Conference on Computer Design (ICCD), pages 417-424, Oct. 2010, pdf at TU München: mediaTUM page
A. Bartolini, M. Cacciari, A. Tilli, L. Benini, M. Gries: A Virtual Platform Environment for Exploring Power, Thermal and Reliability Management Control Strategies in High-performance Multicores, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 311-316, May 2010
I am one of 30 authors (nine authors from Intel Labs Braunschweig): A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS, IEEE Int. Solid-State Circuits Conference (ISSCC), session 5.7, pages 108-109, Feb. 2010
H.-P. Löb, M. Gries, C. Sauer: Implementing a Software-based 802.11 MAC on a Customized Platform, 6th IEEE Consumer Communications & Networking Conference (CCNC), pages 1-6, Jan. 2009
C. Sauer, M. Gries, H.-P. Löb: SystemClick: A Domain-specific Framework for Early Exploration Using Functional Performance Models, 45th Design Automation Conference (DAC), pages 480-485 (session 27: advanced wireless design), June 2008
C. Sauer, M. Gries, S. Dirk: Hard- and Software Modularity of the NOVA MPSoC Platform, Design, Automation & Test in Europe (DATE), pages 1102-1107, April 2007, pdf at DATE site
S. Sonntag, M. Gries, C. Sauer: Performance Evaluation of Packet Processing Architectures using Multiclass Queuing Networks, 39th Annual Simulation Symposium (ANSS), pages 80-89, April 2006
C. Sauer, M. Gries, S. Sonntag, D. Tolle, B. Wu, R. Knorr: Trends in Access Networks and their Implementation in DSLAMs, 30th IEEE Conf. on Local Computer Networks (LCN), pages 493-494, Nov. 2005
C. Sauer, M. Gries, S. Sonntag: Modular Reference Implementation of an IP-DSLAM, 10th IEEE Symposium on Computers and Communications (ISCC), pages 191-198, June 2005, pdf: dslam_bench_iscc05.pdf
C. Sauer, M. Gries, S. Sonntag: Modular Domain-Specific Implementation and Exploration Framework for Embedded Software Platforms, 42nd Design Automation Conference (DAC), pages 254-259, June 2005
S.J. Weber, M.W. Moskewicz, M. Gries, C. Sauer, K. Keutzer: Fast Cycle-Accurate Simulation and Instruction Set Generation for Constraint-Based Descriptions of Programmable Architectures, International Conference on Hardware/Software Codesign (CODES), pages 18-23, Stockholm, Sweden, Sep. 2004
C. Sauer, M. Gries, J.I. Gomez, S. Weber, K. Keutzer: Developing a Flexible Interface for RapidIO, Hypertransport, and PCI-Express, 4th International Conference on Parallel Computing in Electrical Engineering (parelec), pages 129-134, Dresden, Germany, Sep. 2004
C. Kulkarni, M. Gries, C. Sauer, K. Keutzer: Programming Challenges in Network Processor Deployment, Int. Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), pages 178-187, Oct. 2003
M. Gries, C. Kulkarni, C. Sauer, K. Keutzer: Comparing Analytical Modeling with Simulation for Network Processors: A Case Study, Design, Automation, and Test in Europe (DATE), Munich, Germany, pages 256-261, March 2003, pdf at DATE site
S. Chakraborty, M. Gries, L. Thiele: Supporting a Low Delay Best-Effort Class in the Presence of Real-Time Traffic, 8th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), San Jose CA, pages 45-54, Sep. 2002, pdf: rtas_cgt02.pdf
L. Thiele, S. Chakraborty, M. Gries, S. Künzli: A Framework for Evaluating Design Tradeoffs in Packet Processing Architectures, 39th Design Automation Conference (DAC 2002), New Orleans LA, USA, pages 880-885, June 2002, pdf at ETHZ: TCGK02b.pdf
L. Thiele, S. Chakraborty, M. Gries, A. Maxiaguine, J. Greutert: Embedded Software in Network Processors - Models and Algorithms, First Workshop on Embedded Software (EMSOFT), Lake Tahoe CA, USA, Lecture Notes in Computer Science 2211, Springer-Verlag, pages 416-434, Oct. 2001, pdf at ETHZ: TCG01a.pdf
M. Gries: The Impact of Recent DRAM Architectures on Embedded Systems Performance, Euromicro'2000, 26th Symposium on Digital Systems Design, Maastricht, Netherlands, vol. 1, pages 282-289, IEEE Computer Soc., Sep. 2000, pdf at ETHZ: Gri00b.pdf, Abstract
M. Gries, J.W. Janneck, M. Naedele: Reusing Design Experience for Petri Nets through Patterns, High Performance Computing Symposium '99 (HPC99), San Diego CA, USA, pages 453-458, April 1999, pdf at ETHZ: GJN99a.pdf
L. Stanisic, R. Mijakovic, M. Gries: Performance Evaluation of the Ginkgo Sparse Linear Solver Framework on Arm, talk only, Arm HPC User Group (AHUG) workshop at ISC High Performance conference, Hamburg, Germany, May 2023, pdf at AHUG github: ISC23-AHUG_Luka-Stanisic.pdf
M. Gries: Accelerating the Future of Manycore Software with the Single-chip Cloud Computer (SCC) - a 48 Core Research Microprocessor, talk only, 3rd workshop on Emerging Applications and Many-Core Architecture (EAMA) at the 37th Int. Symposium on Computer Architecture (ISCA), St. Malo, France, June 2010
C. Sauer, M. Gries, J.-C. Niemann, M. Porrmann, M. Thies: Application-driven Development of Concurrent Packet Processing Platforms, 5th Int. Symposium on Parallel Computing in Electrical Engineering (PARELEC), pages 55-61, Sept. 2006
C. Sauer, M. Gries, S. Dirk: Modularity and Programmability of the NOVA Packet Processing Platform, Advanced Networking and Communications Hardware Workshop (ANCHOR) at the 33rd Int. Symposium on Computer Architecture (ISCA), pages 43-52, Boston, MA, June 2006
H.-M. Bluethgen, C. Sauer, M. Gries, W. Raab, D. Langen, A. Schackow, M. Loew, U. Hachmann, N. Bruels, U. Ramacher: Finding the Optimum Partitioning for Multi-Standard Radio Systems, Software Defined Radio Technical Conference, Session 1.5, Orange County, CA, Nov. 2005
H.-M. Blüthgen, C. Sauer, D. Langen, M. Gries, W. Raab: Application-Driven Design of Cost-Efficient Communications Platforms, workshop on methods for nanometer VLSI design, Informatik 2005, pages 314-318, Sep. 2005
S. Sonntag, M. Gries, C. Sauer: Performance Evaluation of VLSI platforms using SystemQ, workshop on methods for nanometer VLSI design, Informatik 2005, pages 319-323, Sep. 2005
S. Sonntag, M. Gries, C. Sauer: SystemQ: A Queuing-Based Approach to Architecture Performance Evaluation with SystemC, SAMOS V: Embedded Computer Systems: Architectures, MOdeling, and Simulation, Springer LNCS 3553, pages 434-444, July 2005
C. Sauer, M. Gries, J.I. Gomez, K. Keutzer: Towards a Flexible Network Processor Interface for RapidIO, Hypertransport, and PCI-Express, 3nd Workshop on Network Processors (NP3) at the 10th International Symposium on High Performance Computer Architecture (HPCA10), Madrid, Spain, pages 26-39, Feb. 2004
M. Gries, C. Kulkarni, C. Sauer, K. Keutzer: Exploring Trade-offs in Performance and Programmability of Processing Element Topologies for Network Processors, 2nd Workshop on Network Processors (NP2) at the 9th International Symposium on High Performance Computer Architecture (HPCA9), Anaheim CA, USA, pages 75-87, Feb. 2003
L. Thiele, S. Chakraborty, M. Gries, S. Künzli: Design Space Exploration of Network Processor Architectures, First Workshop on Network Processors at the 8th International Symposium on High-Performance Computer Architecture (HPCA8), Cambridge MA, USA, pages 30-41, Feb. 2002, pdf at ETHZ: TCGK02a.pdf
M. Gries: Modeling a Memory Subsystem with Petri Nets: a Case Study, Workshop Hardware Design and Petri Nets '98 (HWPN98), Lisbon, Portugal, pages 186-201, June 1998, pdf at ETHZ: gri98a.pdf; Abstract
M. Gries: Joint Evaluation of Architecture and Behavior for Network Processing Systems, unpublished technical report, Computer Engineering and Networks Laboratory (TIK), ETH Zurich, Switzerland, June 2006, pdf (put online July 2018; the report summarizes and updates the evaluation in my PhD thesis): TR-network_processing_evaluation-mgries-2006.pdf
C. Sauer, M. Gries, S. Sonntag: Next-Generation Network Access Platform, Infineon Research Trends, Special Issue on Systems and Applications, pages 34-40, Munich, Jan. 2005
M. Gries, S. Weber, C. Brooks: The Mescal Architecture Development System (Tipi) Tutorial, UCB/ERL Technical Memorandum M03/40, Electronics Research Laboratory, University of California at Berkeley, Oct. 2003
M. Gries: Methods for Evaluating and Covering the Design Space during Early Design Development, UCB/ERL Technical Memorandum M03/32, Electronics Research Laboratory, University of California at Berkeley, Aug. 2003, pdf: ucb-erl_m03-32_DSE_survey.pdf, Abstract
C. Sauer, M. Gries, C. Kulkarni, K. Keutzer: Performance Analysis of the Peripheral-Processor Interaction in Embedded Systems, UCB/ERL Technical Memorandum M03/26, Electronics Research Laboratory, University of California at Berkeley, June 2003
S. Chakraborty, M. Gries, L. Thiele: Supporting a Low Delay Best-Effort Class in the Presence of Real-Time Traffic, TIK-Report No. 131, Computer Engineering and Networks Laboratory (TIK), ETH Zurich, Switzerland, March 2002, ps: TIK-Report131.ps
M. Gries, J. Greutert: Modeling a Shared Medium Access Node with QoS Distinction, TIK-Report No. 86, Computer Engineering and Networks Laboratory (TIK), ETH Zurich, Switzerland, April 2000, pdf: TIK-Report86.pdf
M. Gries, A. Romer: Performance Evaluation of Recent DRAM Architectures for Embedded Systems, TIK-Report No. 82, Computer Engineering and Networks Laboratory (TIK), ETH Zurich, Switzerland, Nov. 1999, pdf: TIK-Report82.pdf
M. Gries: A Survey of Synchronous RAM Architectures, TIK-Report No. 71, Computer Engineering and Networks Laboratory (TIK), ETH Zurich, Switzerland, April 1999, pdf: TIK-Report71.pdf; Abstract
PhD thesis: see publications (M. Gries: Algorithm-Architecture Trade-offs in Network Processor Design, Ph.D. thesis, Computer Engineering and Networks Laboratory (TIK) , ETH Zurich, Switzerland, ETH Diss. No. 14191, Shaker Verlag Aachen, Germany, July 2001, ISBN 3-8265-9044-9)
Diploma thesis: Rekonfigurierbare Rechnerarchitekturen für H.263 (reconfigurable computer architectures for ITU-T H.263), AB Technische Informatik I (Computer Engineering), Technical University of Hamburg-Harburg, Germany, Oct 1996
Short term thesis: Aufnahme von Ströhmungsbildern und Implementierung von Algorithmen zur Ermittlung der Ströhmungsgeschwindigkeit (implementation of algorithms for fluid velocity determination by image processing of photographs), AB Technische Informatik I (Computer Engineering), Technical University of Hamburg-Harburg, Germany, Jul 1995
P. Falk, M. Gries, F. Herold, Qinfei Liu, M. Marchenko, Troy Patterson: Performance Evaluation of the BeeGFS File System on the Arm AArch64 Architecture, whitepaper, May 2022; available at ThinkParQ (external link)
Research@Intel in Europe Day demonstration: Realtime DDR3 Programmable Memory Traffic Analyzer, Leixlip, Ireland, Oct. 2011
CeBIT'06 computer trade show demonstration: DSLAM access network platform demonstrator, Infineon Technologies together with Fraunhofer Institute and University of Paderborn, exhibition hall 09, BMBF booth B40 (German Federeal Ministry of Education and Research), Hannover, Germany, March 2006; Read more here
C. Sauer, M. Gries, S. Dirk, J.-C. Niemann, M. Porrmann, U. Rückert: A Lightweight NoC for the NOVA Packet Processing Platform, workshop on Future Interconnects and Networks on Chip, DATE, Munich, Germany, March 2006, pdf: NOVA_date06.pdf
S. Sonntag, M. Gries, C. Sauer, R. Thudt: Performance Evaluation of Embedded Systems using SystemQ, Infineon Embedded Software Days (IESD) poster, Munich, Germany, October, 2005
C. Sauer, M. Gries, S. Sonntag: CRACC: A Modular Domain-Specific Implementation and Exploration Framework for Embedded Software Platforms, Infineon Embedded Software Days (IESD) poster, Munich, Germany, October, 2005
C. Sauer, M. Gries, G. Hagen, S. Sonntag, W. Brunnbauer: Specification and Design of an IP-DSLAM Using a Modular Approach, Infineon Embedded Software Days (IESD) poster, Bangalore, India, Sept. 2004