(Intel Germany Research Center [IGRC], Germany Microprocessor Lab)
Research related to the memory hierarchy include DRAM-specific controllers, shared and distributed cache hierarchies and their impact on memory traffic due to coherence, as well as more forward looking non-uniform memory architectures for highly concurrent and heterogeneous Systems-on-Chip. Choices of the architecture can impact the resilience and security of the system as well as the programming model (e.g., software-managed scratchpad memories).
If we face the implications of terascale systems for mainstream computing within the next decade, we will have to handle highly concurrent and heterogeneous chip architectures that will be constrained by power dissipation and thermal limits (e.g., by power density leading to on-chip hot spots). Traditionally, thermal, power, and workload management have been treated separately to optimize for performance and energy efficiency. In the era of terascale where chip architectures will easily have 64+ manageable processing and communication resources (processors, accelerators, caches, buses, memory channels) new integrated approaches are needed to fully use these architectures by orchestrating individual workload, power, and performance states.
I am a member of the DDR3 memory
controller team responsible for specification, design and validation of
the four controllers in SCC implemented in 45nm. Intel Labs announced
the experimental chip on Dec. 2nd 2009 at several locations including Braunschweig
and San Francisco. Details of the chip were presented at ISSCC in Feb. 2010 and two
symposia. Technical material about SCC can be found at Intel at http://www.intel.com/info/scc
. I gave a talk about SCC at the 3rd workshop on Emerging Applications
and Many-Core Architecture (EAMA) at
the 37th
Int. Symposium on Computer Architecture (ISCA) in June 2010.
M. Gries, U. Hoffmann, M. Konow, M. Riepen: SCC: A Flexible Architecture for Many-Core Platform Research, Novel Architectures Column, Computing in Science and Engineering, vol. 13(6), pages 79-83, Nov./Dec. 2011
J. Howard, S. Dighe, S.R. Vangal, G. Ruhl, N. Borkar, S. Jain, V. Erraguntla, M. Konow, M. Riepen, M. Gries, G. Droege, T. Lund-Larsen, S. Steibl, S. Borkar, V.K. De, R. Van Der Wijngaart: A 48-Core IA-32 Processor in 45nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling, IEEE Journal of Solid State Circuits (JSSC), vol. 46(1), pages 173-183, Jan. 2011
B. Dietrich, S. Nunna, D. Goswami, S. Chakraborty, M. Gries: LMS-based Low-Complexity Game Workload Prediction for DVFS, 28th IEEE Int. Conference on Computer Design (ICCD), pages 417-424, Oct. 2010
A. Bartolini, M. Cacciari, A. Tilli, L. Benini, M. Gries: A Virtual Platform Environment for Exploring Power, Thermal and Reliability Management Control Strategies in High-performance Multicores, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 311-316, May 2010