Projects at Intel Labs Braunschweig

(Intel GmbH, Germany Microprocessor Lab, Braunschweig)

Matthias Gries, Sr. research scientist, 2007 to 2014

HW-SW cross-layer optimization for new memory technologies

My research includes assessing the implications of future DRAM (like eDRAM, graphics RAM and HBM) and Non-Volatile Memory (NVM) technologies (such as Phase-Change Memory [PCM], 3DXPoint and Spin-Transfer Torque [STT] RAM) on the organization in several levels of a memory hierarchy, including software layers. My contributions lie in designing individual controller features to whole memory subsystem setups to orchestrate the movement of data based on design objectives for energy efficiency, performance and costs. Choices of the architecture can impact the resilience and security of the system, as well as the programming model (e.g., for software-managed persistent memories). My evaluations are based on co-emulation of hardware and software components with FPGAs and system simulators in order to assess the benefits of in-memory computing, data mining & analytics, and responsiveness by leveraging large capacity, durable, byte-addressable NVM RAM for handheld (tablet, smartphone) and server applications. 

Application-driven resource management 

If we face the implications of System-on-Chip architectures within the next decade, we will have to handle highly concurrent and heterogeneous chip architectures that will be constrained by power dissipation and thermal limits. Traditionally, thermal, power and workload management have been treated separately to optimize for performance and energy efficiency. High-end SoC architectures already have 50+ manageable processing and communication resources (processors, accelerators, caches, buses, memory channels), such that new integrated approaches are needed to fully use these architectures by orchestrating individual workload, power and performance states. I particularly investigate the impact of application-level profiling and instrumentation steps in control by the programmer (such as access to dynamic voltage and frequency scaling [DVFS] and sensorial input) to steer lower-level resource management decisions, together with partners at the University of Bologna, University of Edinburgh and TU München. 

SCC: Single-chip Cloud Computer (link to Intel's description) experimental manycore processor

I was a member of the DDR3 memory controller team responsible for specification, design and validation of the four controllers in SCC implemented in 45nm. Intel Labs announced the experimental chip on Dec. 2nd 2009 at several locations including Braunschweig and San Francisco. Details of the chip were presented at ISSCC in Feb. 2010 and two symposia. Technical material about SCC was shared in Intel's former MARC community (communities.intel.com/community/marc).

I gave a talk about the SCC at the 3rd workshop on Emerging Applications and Many-Core Architecture (EAMA) at the 37th Int'l Symposium on Computer Architecture (ISCA) in June 2010. I also regularly reviewed contributions to Intel's Manycore Applications Research Community (MARC) and associated symposia from 2010 to '13.

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