Former Projects at Infineon Technologies

Matthias Gries, Corporate Research and Communication Solutions departments, 2004 to 2007

We investigated the implications of providing an application-specific multi-processor platform for network processing that can easily be exploited (i.e., programmed) by the customer. This view requires modifications to existing programming views (assembly for the most part) and the hardware architecture. This project is partly funded by the German Federal Ministry of Education and Research (BMBF).

CRACC code generation for embedded processors

Our CRACC code generators use the Click modular router language as input and instantiate C-library elements accordingly. The Click programming view is a natural specification for network applications since the underlying concurrency of packet flows is exposed to the programmer and queuing stages are explicit. Results on the efficiency of CRACC are promising in terms of performance and code size, as shown in our paper at DAC'05. Heterogeneous multiprocessor targets are supported by platform-specific Click elements, e.g. for encapsulating bus access logic, and a thin OS layer for, e.g., shared memory allocation. The programmer partitions the Click graph manually at Click element boundaries onto several processing elements. This mapping information is an additional annotation in the Click graph. These mechanisms are shown in our paper at DATE'07.

NOVA (Network Optimized Versatile Architecture)

The main idea is to provide an open and modular platform architecture. This means, commodity parts are used wherever possible and application-specific modifications are applied where needed due to constraints on performance and costs. Our application-driven design methodology starts with a systematic analysis of the application domain and the definition of executable reference applications (benchmarks) described in Click. We then start with the most flexible (i.e. most programmable in our case) platform as a starting point for the refinement of the platform architecture. One application-specific design decision that we made at the very beginning is to implement message passing between processing elements in hardware so that the Click communication semantics can easily be matched with the behavior of the underlying hardware. These ideas have been introduced at a poster presentation at DATE'06.

CeBIT'06 trade fair demonstration

We have shown an initial NOVA prototype at the CeBIT'06 trade fair in Hannover, Germany, at the booth of the German Federal Ministry of Education and Research (BMBF). The prototype consists of four processing elements and their subsystem (local memories and coprocessors), shared memory, and four fast Ethernet network interfaces. The network application is described in Click and firmware is generated by using CRACC. Read more here

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