02/97 - 05/01

Ph.D. (Doctor of Technical Sciences) ETH Zürich, Computer Engineering and Networks Laboratory, Switzerland.
Examiners: Prof. Lothar Thiele, Prof. Wolfgang Fichtner
Thesis: Algorithm-Architecture Trade-offs in Network Processor Design.

10/91 - 12/96

Dipl.-Ing. degree (M.Sc. equivalent) in Electrical Engineering, Technical University of Hamburg-Harburg (TUHH), Germany.
Thesis: Reconfigurable Computer Architectures for the Video Codec ITU H.263.
Studies of Electrical Engineering with focus on digital signal processing (communications).

since 04/07

Intel GmbH, Intel Labs Braunschweig, Germany.
Systems Technology Lab; since June'09 Microprocessor and Programming Research/Germany Microprocessor Lab (GML).
Design methods and architectures for memory subsystems and platform resource management.

07/04 - 03/07

Infineon Technologies, Corporate Research & Communication Solutions, Munich, Germany.
Networked systems & processor architectures.
Benchmark definition and implementation, design of SoC components for multiprocessor platform, implementation of programming models for embedded platforms.

05/02 - 06/04

University of California at Berkeley, CAD group, Prof. Kurt Keutzer, post-doc researcher.
Mescal project, funded by GSRC and Infineon Technologies.
Methods for design space exploration of network processors and ASIP design. 

02/97 - 04/02

ETH Zürich, Computer Engineering and Networks Laboratory, Switzerland, research assistant.
IP Cube project with Inalp Networks on QoS in network processors, funded by the Swiss Commission for Technology and Innovation (KTI).
Teaching assistant for classes on Hardware-Software Codesign, Computer Architecture, Operating Systems, and Embedded Systems Design.