See also class 290a and the Mescal page at UC Berkeley.
I worked on methods for systematically exploring the design space of network processors. This was a continuation of the network calculus based work at ETH Zurich and finally resulted in a survey article on design space exploration in Elsevier's VLSI journal at the end of 2004.
I also contributed to the Architecture Development System Tipi where I worked on the intuitive representation of operations to ease the definition of Instruction Set Architectures for ASIPs (screenshot). We published a book on the Mescal methodology for ASIP design in 2005.
M. Gries, K. Keutzer (editors): Building ASIPs: The Mescal Methodology, Springer, 375 pages, June 2005, ISBN: 0-387-26057-9
M. Gries: Methods for Evaluating and Covering the Design Space during Early Design Development, Integration, the VLSI Journal, Elsevier, vol. 38(2), pages 131-183, 2004
S.J. Weber, M.W. Moskewicz, M. Gries, C. Sauer, K. Keutzer: Fast Cycle-Accurate Simulation and Instruction Set Generation for Constraint-Based Descriptions of Programmable Architectures, International Conference on Hardware/Software Codesign (CODES), pages 18-23, Stockholm, Sweden, Sep. 2004
M. Gries, C. Kulkarni, C. Sauer, K. Keutzer: Exploring Trade-offs in Performance and Programmability of Processing Element Topologies for Network Processors, Network Processor Design: Issues and Practices, volume 2, Editors: P. Crowley, M. Franklin, H. Hadimioglu, P. Onufryk, Morgan Kaufmann Publishers, pages 133-158, Nov. 2003