In an R&D role on programmable System-on-Chips (SoCs) and their software ecosystems, Matthias Gries assesses the feasibility of core/uncore technologies (technology pathfinding) subject to domain-specific software stacks by analyzing trends, modeling & simulation of new architectures, benchmarking on real systems, and evaluating power, performance, area, usability trade-offs.

At Cyberus Technology, he analyzes confidential computing CPU technologies with implications on cloud and edge use cases, usability, interplay with complementary security approaches, as well as technology readiness subject to regulatory conditions.

At Huawei Technologies in Munich, Germany, as Principal Engineer from 2015 to 2024, he was responsible for developing CPU technologies and memory system solutions targeted at enterprise IT hardware and Arm AArch64 enabled products, as well as strengthening their software ecosystem for scientific computing/HPC. From 2007 to 2014, he drove the development of integrated hardware-software technologies for memory subsystems, manycore, and platform resource management at Intel in Braunschweig, Germany. Before, he spent three years at Infineon Technologies in Munich, Germany, implementing microarchitectures and programming views for network applications at the Corporate Research and Communication Solutions departments. He was a post-doctoral researcher at the University of California, Berkeley, in the Computer-Aided Design group, refining design methods for application-specific programmable processors from 2002 to '04. He received the Doctor of Technical Sciences degree from the Swiss Federal Institute of Technology (ETH) Zurich in 2001 for the system-level design of a QoS network processor. He received the Dipl.-Ing. degree in electrical engineering from the Technical University Hamburg-Harburg, Germany, in 1996.

His interests include hardware and CPU architectures, design methods, support in the software stack for tailoring platform solutions, application-specific processors and MP SoCs, network processing, and system-level design.